Decoupling capacitance allocation for timing with statistical noise model and timing analysis

Authors:
Takashi Enami;Masanori Hashimoto;Takashi Sato
Affiliations:
Osaka University, Suita, Osaka, Japan;Osaka University, Suita, Osaka, Japan;Tokyo Institute of Technology, Nagatsuta, Midori-ku, Yokohama, Japan
Venue:
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Year:
2008

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Abstract

This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a gate delay at all the switching timing within a cycle, and devised an efficient sensitivity calculation of timing to decap for decap allocation. The proposed method, which is based on a statistical noise modeling and timing analysis, accelerates the sensitivity calculation with an approximation and adjoint sensitivity analysis. Experimental results show that the decap allocation based on the sensitivity analysis efficiently optimizes the worst-case circuit delay within a given decap budget. Compared to the maximum decap placement, the delay improvement due to decap increases by 5% even while the total amount of decap is reduced to 40%.