First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
STAC: statistical timing analysis with correlation
Proceedings of the 41st annual Design Automation Conference
Timing
Timing analysis considering spatial power/ground level variation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Static timing analysis considering power supply variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
On-chip measurement system for within-die delay variation of individual standard cells in 65-nm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integration, the VLSI Journal
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This paper proposes a gate delay model that is suitable for timing analysis considering wide-range process and environmental variability. The proposed model focuses on current variation and its impact on delay is considered by replacing output load. The proposed model is applicable for large variability with current model constructed by DC analysis whose cost is small. The proposed model can also be used both in statistical static timing analysis and in conventional corner-based static timing analysis. Experimental results in a 90nm technology show that the gate delays of inverter, NAND and NOR are accurately estimated under gate length, threshold voltage, supply voltage and temperature fluctuation. We also verify that the proposed model can cope with slow input transition and RC output load. We demonstrate applicability to multiple-stage path delay and flip-flop delay, and show an application of sensitivity calculation for statistical timing analysis.