An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS

Authors:
Xin Zhang;Koichi Ishida;Makoto Takamiya;Takayasu Sakurai
Affiliations:
University of Tokyo, Meguro-ku, Tokyo, Japan;University of Tokyo, Meguro-ku, Tokyo, Japan;University of Tokyo, Meguro-ku, Tokyo, Japan;University of Tokyo, Meguro-ku, Tokyo, Japan
Venue:
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Year:
2011

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On-chip measurement system for within-die delay variation of individual standard cells in 65-nm CMOS

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Abstract

New characterizing system for within-die delay variations of individual standard cells is presented. The proposed characterizing system is able to measure rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65nm CMOS process. 7 types of standard cells are measured with 60 DUT's for each type. Thanks to the proposed system, a relationship between the rising and falling delay variations and the active area of the standard cells is experimentally shown for the first time.