Clock and Power Gating with Timing Closure

Authors:
Arindam Mukherjee;Malgorzata Marek-Sadowska
Affiliations:
University of North Carolina at Charlotte;University of California, Santa Barbara
Venue:
IEEE Design & Test
Year:
2003

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Abstract

Editor's note:Assuming that delay is linearly dependent on local power supply voltage, the authors show how to set up an analysis to determine the effect of power supply variations on delay. This analysis can drive the introduction of clock gating, an increasingly popular technique for reducing dynamic power dissipation.ýSani R. Nassif, IBM Austin Research Laboratory