Implementing Asynchronous Circuits on LUT Based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Clock and Power Gating with Timing Closure
IEEE Design & Test
An Asynchronous Dataflow FPGA Architecture
IEEE Transactions on Computers
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Measurement of power supply noise tolerance of self-timed processor
DDECS '09 Proceedings of the 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits&Systems
Quasi-static voltage scaling for energy minimization with time constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A 65nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signalling allows the FPGA to operate at voltages down to 370mV without any parameter tuning. We show both 2.6x total energy reduction and 6.4x performance improvement at the same time for energy minimum operation compared to the non-power gated SSFPGA, and compared to the latest research 1.8x improvement in power delay product (PDP) and 2x performance improvement. When compared to a synchronous FPGA in a similar process we are able to show up to 84.6x PDP improvement. We also show energy minimum operation for maximum throughput on the power gated SSFPGA is achieved at 0.6V, 27fJ/operation at 264MHz.