Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Reliable non-zero skew clock trees using wire width optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Optimal wiresizing under the distributed Elmore delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 37th Annual Design Automation Conference
Current signature compression for IR-drop analysis
Proceedings of the 37th Annual Design Automation Conference
Worst case clock skew under power supply variations
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clock skew verification in the presence of IR-drop in the power distribution network
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variation tolerant buffered clock network synthesis with cross links
Proceedings of the 2006 international symposium on Physical design
Cross link insertion for improving tolerance to variations in clock network synthesis
Proceedings of the 2011 international symposium on Physical design
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In this paper, we present a novel approach to the problem of clock skew minimization by buffer and wire sizing. The original nonlinear programming problem is transformed to a sequence of linear programs, by taking the first order Taylor's expansion of clock path delay with respect to buffer and wire widths. The sensitivities of clock path delay, with respect to buffer and wire widths, are efficiently updated for each linear program by applying time domain analysis to the clock network in a divide-and-conquer fashion. Our technique can take into account the power supply variations, which have significant impact on clock skew. We demonstrate experimentally that in several iterations, the proposed technique is capable of reducing substantially the skew of clock networks.