A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Clock network sizing via sequential linear programming with time-domain analysis
Proceedings of the 2004 international symposium on Physical design
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Improved algorithms for link-based non-tree clock networks for skew variability reduction
Proceedings of the 2005 international symposium on Physical design
Variation tolerant buffered clock network synthesis with cross links
Proceedings of the 2006 international symposium on Physical design
Practical techniques to reduce skew and its variations in buffered clock networks
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees
Proceedings of the International Conference on Computer-Aided Design
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Proceedings of the International Conference on Computer-Aided Design
Low-power buffered clock tree design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
On construction low power and robust clock tree via slew budgeting
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Crosslink insertion for variation-driven clock network construction
Proceedings of the great lakes symposium on VLSI
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Local merges for effective redundancy in clock networks
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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Cross links have been used to reduce skew variations in clock trees. In earlier studies cross links are inserted between the sinks of DC-connected trees. In this paper, we propose a link insertion scheme that inserts cross links between internal nodes of a clock tree. In addition to reducing the skew variability, the proposed approach also reduces the total cross link length. Our work also improves the correlation of sink delays for those sinks within a subtree that have similar path lengths to the cross link. Monte-Carlo (MC) simulations on the ISPD-2010 benchmarks showed that our work could handle variations effectively. In addition to meeting all the design constraints, the solutions produced by our approach have on the average 32% lower capacitance than the least capacitance obtained by the top three teams in the ISPD-2010 design contest [1].