Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
Yield Optimization by Design Centering and Worst-Case Distance Analysis
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Statistical Clock Skew Analysis Considering Intra-Die Process Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Impact of Interconnect Process Variations on Memory Performance and Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 42nd annual Design Automation Conference
A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Design for Manufacturability and Yield for Nano-Scale CMOS
Design for Manufacturability and Yield for Nano-Scale CMOS
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In order for the interconnect effects due to process-induced variations to be applied to the designs in 0.13 μm and below, it is necessary to determine and characterize the realistic interconnect worstcase models with high accuracy and speed. This paper proposes new statistically-based approaches to the characterization of realistic interconnect worstcase models which take into account process-induced variations. The Effective Common Geometry (ECG) and Accumulated Maximum Probability (AMP) algorithms have been developed and implemented into the new statistical interconnect worstcase design environment. To verify this statistical interconnect worstcase design environment, the 31-stage ring oscillators are fabricated and measured with UMC 0.13 μm Logic process. The 15-stage ring oscillators are fabricated and measured with 0.18 μm standard CMOS process for investigating its flexibility in other technologies. The results show that the relative errors of the new method are less than 1.00%, which is two times more accurate than the conventional worstcase method. Furthermore, the new interconnect worstcase design environment improves optimization speed by 29.61–32.01% compared to that of the conventional worstcase optimization. The new statistical interconnect worstcase design environment accurately predicts the worstcase and bestcase corners of non-normal distribution where conventional methods cannot do well.