Yield Optimization by Design Centering and Worst-Case Distance Analysis

Authors:
G. S. Samudra;H. M. Chen
Affiliations:
-;-
Venue:
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Year:
1999

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Abstract

Process variations invariably give rise to a parametric yield below 100% for VLSI circuits. Improving the yield by choosing a set of optimum parameter values does not incur any extra cost, and it is a preferred method as it directly translates into profits. This paper presents an efficient and novel method to improve the VLSI parametric yield by selecting optimum parameter values. This method utilizes the Worst-Case Distance Analysis, Design Centering and Gradient-Dependent techniques. One circuit example is presented to demonstrate the optimization scheme.