Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
On applying incremental satisfiability to delay fault testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Explicit computation of performance as a function of process variation
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Test Generation for Global Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Finding a Small Set of Longest Testable Paths that Cover Every Gate
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Criticality computation in parameterized statistical timing
Proceedings of the 43rd annual Design Automation Conference
Incremental criticality and yield gradients
Proceedings of the conference on Design, automation and test in Europe
Statistical path selection for at-speed test
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Synthesizing a representative critical path for post-silicon delay prediction
Proceedings of the 2009 international symposium on Physical design
Recursive Path Selection for Delay Fault Testing
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Statistical multilayer process space coverage for at-speed test
Proceedings of the 46th Annual Design Automation Conference
Pre-ATPG path selection for near optimal post-ATPG process space coverage
Proceedings of the 2009 International Conference on Computer-Aided Design
First-Order Incremental Block-Based Statistical Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the optimality of K longest path generation algorithm under memory constraints
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In the face of large-scale process variations, statistical timing methodology has advanced significantly over the last few years, and statistical path selection takes advantage of it in at-speed testing. In deterministic path selection, the separation of path selection and test generation is known to require time consuming iteration between the two processes. This paper shows that in statistical path selection, this is not only the case, but also the quality of results can be severely degraded even after the iteration. To deal with this issue, we consider testability in the first place by integrating a SAT solver, and this necessitates a new statistical path selection method. Our proposed method is based on a generalized path criticality metric which properties allow efficient pruning. Our experimental results show that the proposed method achieves 47% better quality of results on average, and up to 361x speedup compared to statistical path selection followed by test generation.