ECP- and CMP-aware detailed routing algorithm for DFM

Authors:
Yin Shen;Qiang Zhou;Yici Cai;Xianlong Hong
Affiliations:
EDA Laboratory, Department of Computer Science and Technology, Tsinghua University, Beijing, China;EDA Laboratory, Department of Computer Science and Technology, Tsinghua University, Beijing, China;EDA Laboratory, Department of Computer Science and Technology, Tsinghua University, Beijing, China;EDA Laboratory, Department of Computer Science and Technology, Tsinghua University, Beijing, China
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

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Abstract

In this paper, a novel design-for-manufacture-aware detailed routing algorithm that seeks to minimize the thickness range of the chip surface after copper damascene process is proposed. The paper is based on an electroplating (ECP) and chemical mechanical polishing (CMP) model and predictors for final thickness range are abstracted. The proposed detailed routing is implemented in a W-shape multilevel full-chip routing framework using depth first search and branch-and-bound techniques in maze backtracking. Experimental results show that compared to maze routing (MR) (that does not consider CMP), the improvements in the average metal density standard and the average amount of dummy fill are 12.0% and 6.99% respectively. Compared to density-drivenmaze routing (DMR) that considers only CMP but does not consider ECP, the improvements in the average metal density standard and the average amount of dummy fill are 0.53% and 0.72%, respectively. So, the proposed algorithm can obtain improvement in optimizing CMP while the wire length and vias are not increased clearly and the completion rate is guaranteed. Therefore, the yield of chips is improved.