Optimal post-routing redundant via insertion
Proceedings of the 2008 international symposium on Physical design
Redundant via insertion with wire bending
Proceedings of the 2009 international symposium on Physical design
Enhanced double via insertion using wire bending
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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It is well known that the yield of an integrated circuit can be modeled based on random defect density. In state-of-the-art wafer fabs, continuous defect reduction is a high engineering priority, and as a result they indeed achieve entitlement values for the defect density, as determined by the design rules, equipment set, and their facility characteristics. Even if a wafer fab achieves its entitlement defect density, a comprehensive yield analysis methodology is still required not only to identify any yield excursions, but also to continually find ways for further yield improvements. Whereas in a wafer fab with defect density above its entitlement value, the yield analysis methodology can easily be focused on defect density reduction alone, in the low defectivity wafer fabs different approach needs to be adopted. In this paper, we discuss yield analysis methodologies appropriate for low defectivity wafer fabs.