Circuit analysis, simulation, and design: general aspects of circuit analysis and design
Circuit analysis, simulation, and design: general aspects of circuit analysis and design
Performance-driven Steiner tree algorithm for global routing
DAC '93 Proceedings of the 30th international Design Automation Conference
Rectilinear Steiner trees with minimum Elmore delay
DAC '94 Proceedings of the 31st annual Design Automation Conference
RC interconnect optimization under the Elmore delay model
DAC '94 Proceedings of the 31st annual Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Post routing performance optimization via tapered link insertion and wiresizing
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing under the distributed Elmore delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing for interconnects with multiple sources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An efficient approach to simultaneous transistor and interconnect sizing
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Non-tree routing for reliability and yield improvement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Improved algorithms for link-based non-tree clock networks for skew variability reduction
Proceedings of the 2005 international symposium on Physical design
On old and new routing problems
Proceedings of the 2011 international symposium on Physical design
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Most existing performance-driven and clock routing algorithms construct optimal routing topology for each net individually without considering its routability on the chip, so they can not guarantee performance after all nets are routed. This paper proposes a new approach for post routing performance optimization via multi-link insertion and non-uniform wiresizing, which improves the performance of a net topology obtained from a global routing solution. Unlike previous approaches, it can achieve reduction in both maximum delay and skew to satisfy user specified constraints and minimizes the routing resource consumed. During optimization, the topology of the net is kept routable. Experiments show that link insertion and wiresizing can improve net performance significantly, and among all approaches, multi-link insertion and wiresizing achieves the best performance and area efficiency.