Physical synthesis of bus matrix for high bandwidth low power on-chip communications

Authors:
Renshen Wang;Evangeline F.Y. Young;Ronald Graham;Chung-Kuan Cheng
Affiliations:
University of California, San Diego, La Jolla, CA, USA;The Chinese University of Hong Kong, Hong Kong, China;University of California, San Diego, La Jolla, CA, USA;University of California, San Diego, La Jolla, CA, USA
Venue:
Proceedings of the 19th international symposium on Physical design
Year:
2010

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Abstract

As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of on-chip data throughput is nowadays a critical target for SoC designers. Under this trend, bus matrices are mostly used in current system-on-chips (SoCs) because of their simplicity and good performance. We introduce a bus matrix synthesis flow to optimize on-chip communications, to keep the low delay of buses, reduce power by bus gating, and reduce wires by wire sharing. The proposed algorithms are able to help designers create high capability yet compact and efficient bus matrices for future low power SoCs.