An introduction to parallel algorithms
An introduction to parallel algorithms
Practical Pram Programming
Parallelism in random access machines
STOC '78 Proceedings of the tenth annual ACM symposium on Theory of computing
Building the 4 Processor SB-PRAM Prototype
HICSS '97 Proceedings of the 30th Hawaii International Conference on System Sciences: Advanced Technology Track - Volume 5
QEMU, a fast and portable dynamic translator
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
Fpga-based prototype of a pram-on-chip processor
Proceedings of the 5th conference on Computing frontiers
Outline of RISC-based core for multiprocessor on chip architecture supporting moving threads
CompSysTech '09 Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing
A cycle-count-accurate simulation platform with enhanced design exploration capability
Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques
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Designing a parallel computer architecture for the multi-core on chip environment involves a lot of architectural design issues. Actual hardware design based on ASIC and for demonstrational purposes on FPGA is very expensive method to study the cost of various design choices. Therefore, we have developed a software based simulator MVTsim for multi-core on chip parallel computers. Due to a special theme of our research project, the simulator is oriented towards supporting a very fine-grained moving threads approach. We describe the general software architecture of the multi-core on chip simulator. In the simulator, special emphasis has been put on concisely expressing the problem domain with a general purpose language, the modular structure of the simulator and target architecture, support for flexible combining of different granularity levels of components, and modelling relevant physical delay related properties. We demonstrate our simulator by describing a RISC-based configuration supporting the moving threads approach, and give some initial results concerning running actual programs with our simulator.