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Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A predictive flow control scheme for efficient network utilization and QoS
IEEE/ACM Transactions on Networking (TON)
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements
Proceedings of the 42nd annual Design Automation Conference
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Prediction-based flow control for network-on-chip traffic
Proceedings of the 43rd annual Design Automation Conference
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Predator: a predictable SDRAM memory controller
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Memory scheduling for modern microprocessors
ACM Transactions on Computer Systems (TOCS)
A practical approach of memory access parallelization to exploit multiple off-chip DDR memories
Proceedings of the 45th annual Design Automation Conference
An open-loop flow control scheme based on the accurate global information of on-chip communication
Proceedings of the conference on Design, automation and test in Europe
OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture
Proceedings of the 11th international workshop on System level interconnect prediction
The virtual write queue: coordinating DRAM and last-level cache policies
Proceedings of the 37th annual international symposium on Computer architecture
A Low-Latency and Memory-Efficient On-chip Network
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A Network Congestion-Aware Memory Controller
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Application-aware NoC design for efficient SDRAM access
Proceedings of the 47th Design Automation Conference
An SDRAM-aware router for networks-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
EEEP: an extreme end to end flow control protocol for SDRAM access through networks on chip
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
A network congestion-aware memory subsystem for manycore
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
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In this paper, we present an NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilization and reduce memory latency. Moreover, our multi-scheduling scheme performed by the multiple SDRAM-aware routers helps to achieve better SDRAM performance and save the hardware cost of NoC platform. Experimental results show that our SDRAM-aware router improves memory latency by 18% and memory utilization by 4.9% on average with over 42% saving of gate count of the NoC platform with dual memory subsystem.