Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Mapping and configuration methods for multi-use-case networks on chips
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Prediction-based flow control for network-on-chip traffic
Proceedings of the 43rd annual Design Automation Conference
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
CTC: An end-to-end flow control protocol for multi-core systems-on-chip
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
An SDRAM-aware router for Networks-on-Chip
Proceedings of the 46th Annual Design Automation Conference
Optimal regulation of traffic flows in networks-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient throughput-guarantees for latency-sensitive networks-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
MPSoC platforms face an increasing diversity of traffic requirements due to the interaction between cores. This interaction is driven by the applications run by the user, and leads to the coexistence of the best effort traffic and the guaranteed service traffic in the same platform. We propose Extreme End-to-End Protocol (EEEP) as a new end-to-end flow control protocol to access SDRAMs through a multiport memory controller in NoC-based MPSoCs. Our protocol considers the memory access within a system approach. It exploits the occupancy rate of the requests queue in the memory controller within the policy of the traffic injection at the master Network Interfaces (NIs) level. By controlling the best-effort traffic shape, EEEP improves the bandwidth and the latency of the guaranteed service traffic.