Interior-Point Methods for Nonconvex Nonlinear Programming: Filter Methods and Merit Functions
Computational Optimization and Applications
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
PERMAP: A performance-aware mapping for application-specific SoCs
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
Networks-on-Chips: Theory and Practice
Networks-on-Chips: Theory and Practice
Flow regulation for on-chip communication
Proceedings of the Conference on Design, Automation and Test in Europe
Buffer optimization in network-on-chip through flow regulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EEEP: an extreme end to end flow control protocol for SDRAM access through networks on chip
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
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We have proposed (σ, ρ) -based flow regulation to reduce delay and backlog bounds in SoC architectures, where σ bounds the traffic burstiness and ρ the traffic rate. The regulation is conducted per-flow for its peak rate and traffic burstiness. In this paper, we optimize these regulation parameters in networks on chips where many flows may have conflicting regulation requirements. We formulate an optimization problem for minimizing total buffers under performance constraints. We solve the problem with the interior point method. Our case study results exhibit 48% reduction of total buffers and 16% reduction of total latency for the proposed problem. The optimization solution has low run-time complexity, enabling quick exploration of large design space.