Scalability of relaxed consistency models in NoC based multicore architectures
ACM SIGARCH Computer Architecture News
Optimal regulation of traffic flows in networks-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Buffer optimization in network-on-chip through flow regulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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This book addresses many challenging topics related to the NoC research area. It starts by studying 3D NoC architectures and progresses to a discussion of NoC resource allocation, processor traffic modeling, and formal verification. NoC protocols are examined at different layers of abstraction. Also, several emerging research issues in NoC are highlighted in this book, such as NoC Quality of Service (QoS), testing and verification methodologies, NoC security requirements, and real-time monitoring. The book also tackles power and energy issues in NoC-based designs, as power constraints are currently considered among the bottlenecks that limit embedding more processing elements on a single chip.