Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
DISHA: a deadlock recovery scheme for fully adaptive routing
IPPS '95 Proceedings of the 9th International Symposium on Parallel Processing
A Progressive Approach to Handling Message-Dependent Deadlock in Parallel Computer Systems
IEEE Transactions on Parallel and Distributed Systems
Integrated shared-memory and message-passing communication in the alewife multiprocessor
Integrated shared-memory and message-passing communication in the alewife multiprocessor
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Mapping and configuration methods for multi-use-case networks on chips
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
NoC Topologies Exploration based on Mapping and Simulation Models
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Trends toward on-chip networked microsystems
International Journal of High Performance Computing and Networking
Distributed flit-buffer flow control for networks-on-chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
EEEP: an extreme end to end flow control protocol for SDRAM access through networks on chip
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
BOFAR: buffer occupancy factor based adaptive router for mesh NoCs
Proceedings of the 4th International Workshop on Network on Chip Architectures
| Hi-index | 0.00 |
We propose Connection then Credits (CTC) as a new end-to-end flow control protocol to handle message-dependent deadlocks in networks-on-chip (NoC) for multicore systems-on-chip. CTC is based on the classic end-to-end credit-based flow control protocol but differs from it because it uses a network interface micro-architecture where a single credit counter and a single input data queue are shared among all possible communications. This architectural simplification reduces the area occupation of the network interfaces and increases their design reuse: for instance, the same network interface can be used to connect a core independently of the number of incoming and outgoing communications. CTC, however, requires a handshake preamble to initialize the credit counter in the sender network interface based on the buffering capacity of the receiver network interface. While this necessarily introduces a latency overhead in the transfer of a message, simulationbased experimental results show that the penalty in performance is limited when large messages need to be transferred, thus making CTC a valid solution for particular classes of applications such as video stream processing.