Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
An SDRAM-aware router for Networks-on-Chip
Proceedings of the 46th Annual Design Automation Conference
A3MAP: architecture-aware analytic mapping for networks-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
A network congestion-aware memory subsystem for manycore
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
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In this paper, we propose an application-aware networks-on-chip (NoC) design for efficient SDRAM access. In order to provide short latency for priority memory requests with few penalties, a packet is split into several short packets which then are scheduled by the proposed flow controller in a router. Moreover, our NoC design further improves memory performance by matching application access granularity to SDRAM access granularity. Experimental results show that our application-aware NoC design improves on average 32.7% memory latency for latency-sensitive cores and on average 3.4% memory utilization compared to [1].