Adaptive multiclient network-on-chip memory core: hardware architecture, software abstraction layer, and application exploration

Authors:
Diana Göhringer;Lukas Meder;Stephan Werner;Oliver Oey;Jürgen Becker;Michael Hübner
Affiliations:
Institute for Data Processing and Electronics, Karlsruhe Institute of Technology and Object Recognition Department, Fraunhofer IOSB, Ettlingen, Germany;Institute for Information Processing Technology, Karlsruhe Institute of Technology, Karlsruhe, Germany;Institute for Information Processing Technology, Karlsruhe Institute of Technology, Karlsruhe, Germany;Institute for Information Processing Technology, Karlsruhe Institute of Technology, Karlsruhe, Germany;Institute for Information Processing Technology, Karlsruhe Institute of Technology, Karlsruhe, Germany;Ruhr-University of Bochum, Bochum, Germany
Venue:
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
Year:
2012

Citing 8
Cited 0

Programming the FlexRAM parallel intelligent memory system

Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming
Distinctive Image Features from Scale-Invariant Keypoints

International Journal of Computer Vision
Æthereal Network on Chip: Concepts, Architectures, and Implementations

IEEE Design & Test
Dynamic System Reconfiguration in Heterogeneous Platforms: The MORPHEUS Approach

Dynamic System Reconfiguration in Heterogeneous Platforms: The MORPHEUS Approach
Self-aware memory: managing distributed memory in an autonomous multi-master environment

ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
A bursty multi-port memory controller with quality-of-service guarantees

CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Adaptive Multi-client Network-on-Chip Memory

RECONFIG '11 Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs
Redsharc: a programming model and on-chip network for multi-core systems on a programmable chip

International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents the hardware architecture and the software abstraction layer of an adaptive multiclient Network-on-Chip (NoC) memory core. The memory core supports the flexibility of a heterogeneous FPGA-based runtime adaptive multiprocessor system called RAMPSoC. The processing elements, also called clients, can access the memory core via the Network-on-Chip (NoC). The memory core supports a dynamic mapping of an address space for the different clients as well as different data transfer modes, such as variable burst sizes. Therefore, two main limitations of FPGA-based multiprocessor systems, the restricted on-chip memory resources and that usually only one physical channel to an off-chip memory exists, are leveraged. Furthermore, a software abstraction layer is introduced, which hides the complexity of the memory core architecture and which provides an easy to use interface for the application programmer. Finally, the advantages of the novel memory core in terms of performance, flexibility, and user friendliness are shown using a real-world image processing application.