International Journal of Reconfigurable Computing - Special issue on Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
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This paper presents a novel approach for a memory, which supports the flexibility of an FPGA-based dynamic reconfigurable System-on-Chip consisting of heterogeneous data processing nodes. The memory is accessible via the Network-on-Chip (NoC) and provides a dynamic mapping of address space for the different clients within the network. Different data transfer modes support especially the image processing domain where burst transfers to the processing nodes are required. The presented method and realization overcomes the well known difficulties in FPGA-based multiprocessor systems, which are the restricted on-chip memory and the fact, that normally only one physical channel to an off-chip memory is available.