Strategy for power-efficient design of parallel systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-power and bandwidth-efficient motion estimation IP core design using binary search
IEEE Transactions on Circuits and Systems for Video Technology
Selective search area reuse algorithm for low external memory access motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Motion estimation optimization for H.264/AVC using source image edge features
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
Low-power H.264 video compression architectures for mobile communication
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
An efficient quality-aware memory controller for multimedia platform SoC
IEEE Transactions on Circuits and Systems for Video Technology
Power-rate-distortion analysis for wireless video communication under energy constraints
IEEE Transactions on Circuits and Systems for Video Technology
Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
Rate-Distortion and Complexity Optimized Motion Estimation for H.264 Video Coding
IEEE Transactions on Circuits and Systems for Video Technology
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This paper proposes a data bandwidth-oriented motion estimation design for resource-limited mobile video applications using an integrated bandwidth rate distortion optimization framework. This framework predicts and allocates the appropriate data bandwidth for motion estimation under a limited bandwidth supply to fit a dynamically changing bandwidth supply. The simulation results show that our proposed algorithm can achieve 66% and 41% memory bandwidth savings while maintaining an equivalent rate-distortion performance and meeting real-time targets, when compared with conventional approaches for low-motion and high-motion D1 (704 × 576)-size video, respectively. The final implementation costs 122 K gate counts with TSMC 0.13-µm CMOS technology and consumes 74 mW of power for D1 resolution at 30 frames/s which is 40% of that achieved in previous designs.