Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability

Authors:
Theo Ungerer;Francisco Cazorla;Pascal Sainrat;Guillem Bernat;Zlatko Petrov;Christine Rochange;Eduardo Quinones;Mike Gerdes;Marco Paolieri;Julian Wolf;Hugues Casse;Sascha Uhrig;Irakli Guliashvili;Michael Houston;Floria Kluge;Stefan Metzlaff;Jorg Mische
Affiliations:
University of Augsburg, Augsburg;Barcelona SuperComputing Center , barcelona;Université Paul Sabatier, Toulouse;Rapita Systems L.t.d, York;Honeywell International s.r.o., Brno;Université Paul Sabatier, Toulouse;Barcelona Supercomputing Center, barcelona;University of Augsburg, Augsburg;Barcelona Supercomputing Center, Barcelona;University of Augsburg, Augsburg;Université Paul Sabatier de Toulouse;University of Augsburg;University of Augsburg;Rapita Systems;University of Augsburg;University of Augsburg;University of Augsburg
Venue:
IEEE Micro
Year:
2010

Citing 0
Cited 13

A dynamic instruction scratchpad memory for embedded processors managed by hardware

ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Temporal isolation on multiprocessing architectures

Proceedings of the 48th Design Automation Conference
PRET DRAM controller: bank privatization for predictability and temporal isolation

CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Real-time wait-free queues using micro-transactions

Proceedings of the 9th International Workshop on Java Technologies for Real-Time and Embedded Systems
On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments

ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Deterministic execution model on COTS hardware

ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions

ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
A hard real-time capable multi-core SMT processor

ACM Transactions on Embedded Computing Systems (TECS)
Bounding WCET of applications using SDRAM with priority based budget scheduling in MPSoCs

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Time analysable synchronisation techniques for parallelised hard real-time applications

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging transactional memory for a predictable execution of applications composed of hard real-time and best-effort tasks

Proceedings of the 21st International conference on Real-Time Networks and Systems
Impact of resource sharing on performance and performance prediction: a survey

CONCUR'13 Proceedings of the 24th international conference on Concurrency Theory
Building timing predictable embedded systems

ACM Transactions on Embedded Computing Systems (TECS)

Quantified Score

Hi-index	0.00

Visualization

Abstract

The Merasa project aims to achieve a breakthrough in hardware design, hard real-time support in system software, and worst-case execution time analysis tools for embedded multicore processors. The project focuses on developing multicore processor designs for hard real-time embedded systems and techniques to guarantee the analyzability and timing predictability of every feature provided by the processor.