Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
A Java processor architecture for embedded real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
Time-predictable Cache Organization
STFSSD '09 Proceedings of the 2009 Software Technologies for Future Dependable Distributed Systems
Hardware support for WCET analysis of hard real-time multicore systems
Proceedings of the 36th annual international symposium on Computer architecture
Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Data caching, garbage collection, and the Java memory model
Proceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst-case execution time analysis for a Java processor
Software—Practice & Experience
A real-time Java chip-multiprocessor
ACM Transactions on Embedded Computing Systems (TECS)
Application requirements and efficiency of embedded Java bytecode multi-cores
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
The embedded Java benchmark suite JemBench
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
A Time-Predictable Object Cache
ISORC '11 Proceedings of the 2011 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing
An Analyzable Memory Controller for Hard Real-Time CMPs
IEEE Embedded Systems Letters
Worst-case execution time analysis-driven object cache design
Concurrency and Computation: Practice & Experience
Data cache organization for accurate timing analysis
Real-Time Systems
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Real-time systems need a time-predictable execution platform to be able to determine the worst-case execution time statically. In order to be time-predictable, several advanced processor features, such as out-of-order execution and other forms of speculation, have to be avoided. However, just using simple processors is not an option for embedded systems with high demands on computing power. In order to provide high performance and predictability we argue to use multiprocessor systems with a time-predictable memory interface. In this paper we present the scalability of a Java chip-multiprocessor system that is designed to be time-predictable. Adding time-predictable caches is mandatory to achieve scalability with a shared memory multi-processor system. As Java bytecode retains information about the nature of memory accesses, it is possible to implement a memory hierarchy that takes the characteristics of different types of accesses into account. For tasks with low communication the measured speedup of this time-predictable system is in the range of 6 to 7 for eight processor cores, compared to execution on a single-core processor.