Java Virtual Machine Specification
Java Virtual Machine Specification
A time predictable Java processor
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An object-aware memory architecture
Science of Computer Programming - Special issue on five perspectives on modern memory management: Systems, hardware and theory
SableVM: a research framework for the efficient execution of java bytecode
JVM'01 Proceedings of the 2001 Symposium on JavaTM Virtual Machine Research and Technology Symposium - Volume 1
Enabling constant-time interface method dispatch in embedded Java processors
JTRES '07 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems
Bump-pointer method caching for embedded Java processors
JTRES '07 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems
Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
High Performance Memory Management for a Multi-core Architecture
CIT '09 Proceedings of the 2009 Ninth IEEE International Conference on Computer and Information Technology - Volume 02
WCET driven design space exploration of an object cache
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
The embedded Java benchmark suite JemBench
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
An embedded GC module with support for multiple mutators and weak references
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
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The Java platform promotes the fast development of complex software. For the efficient execution of Java code in embedded systems, multi-core Java processors offer a promising implementation option that is directly capable to exploit thread-level concurrency available in a Java application. This paper explores measures to relieve the critical heap memory interface, which regularly limits the achievable speedup. The described object cache with a supplementing translation lookaside buffer is shown to double the effective speedup in concurrent applications constrained by the memory bandwidth. The investment into additional hardware resources proves to be moderate.