Reliable and Precise WCET Determination for a Real-Life Processor
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
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RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
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CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
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EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
Cross-profiling for Java processors
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Worst-case execution time analysis for a Java processor
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ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
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ACM Transactions on Embedded Computing Systems (TECS)
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Caching of complete methods has been suggested to simplify the determination of the worst-case execution time (WCET) in the presence of a memory hierarchy [9]. While this previous approach limits possible cache misses to method invocations and returns, it still assumes a conventional blocked organization of the cache memory. This paper proposes and evaluates a new approach organizing the cached methods within a linked list while tag matching is limited to a sliding window of at most three methods over this linked list. The main advantages of this approach are the avoidance of low block utilization by small methods through bump-pointer space allocation and a further simplification of the WCET analysis by an easy miss prediction based solely on call stack information available locally.