Increasing the efficiency of an embedded multi-core bytecode processor using an object cache
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
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Architecture and memory system are two important factors that influence the performance of parallel processing systems. This paper based on a proposed real scalable, triple-based multi-core architecture providing hardware level support for object-oriented methodology. However, the Memory Wall is still the bottleneck of the whole system performance. We present Hierarchical Shared Memory (HSM) architecture that is hierarchically constructed memory shared by multi-cores. A new partially-inclusive mapping policy used to map data among different levels of cache and memory, which facilitates the coherence of shared memory. And a novel objects management also proposed. In multi-core systems, all cores share the DRAM bandwidth makes it become a critical shared resource. In order to resolve problems like starvation, complexity, and unpredictable DRAM access latency, we present a DRAM access management scheme—Fair Dynamic Pipelining (FDP) memory access scheduling with two key features. First, the scheme avoids unexpected long latencies or starvation of memory requests using the dynamic pipeline arrangement policy. Second, it provides an alterable priority strategy to make the response of memory more fairly. Comparisons with other common approaches shown that our objects management is predominant in spatial and temporal aspects on memory parallel access efficiency and costs less storage space to organize objects than link structured object organization. The experiment result shown that the FDP scheduling makes the bandwidth shares to achieve desired average latencies for multi cores memory accesses.