Quality of service capabilities for hard real-time applications on multi-core processors
Proceedings of the 21st International conference on Real-Time Networks and Systems
On-chip ring network designs for hard-real time systems
Proceedings of the 21st International conference on Real-Time Networks and Systems
Multi-core composability in the face of memory-bus contention
ACM SIGBED Review
A Unified WCET analysis framework for multicore platforms
ACM Transactions on Embedded Computing Systems (TECS)
Static analysis of multi-core TDMA resource arbitration delays
Real-Time Systems
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In the domain of real-time systems, the analysis of the timing behavior of programs is crucial for guaranteeing the schedulability and thus the safeness of a system. Static analyses of the WCET (Worst-Case Execution Time) have proven to be a key element for timing analysis, as they provide safe upper bounds on a program's execution time. For single-core systems, industrial-strength WCET analyzers are already available, but up to now, only first proposals have been made to analyze the WCET in multicore systems, where the different cores may interfere during the access to shared resources. An important example for this are shared buses which connect the cores to a shared main memory. The time to gain access to the shared bus may vary significantly, depending on the used bus arbitration protocol and the access timings. In this paper, we propose a new technique for analyzing the duration of accesses to shared buses. We implemented a prototype tool which uses the new analysis and tested it on a set of real world benchmarks. Results demonstrate that our analysis achieves the same precision as the best existing approach while drastically outperforming it in matters of analysis time.