The NuMesh: a modular, scalable communications substrate
ICS '93 Proceedings of the 7th international conference on Supercomputing
Hierarchical Ring Network Configuration and Performance Modeling
IEEE Transactions on Computers
Statistical clock skew modeling with data delay variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Journal of Parallel and Distributed Computing
A Performance Comparison of Hierarchical Ring- and Mesh- Connected Multiprocessor Networks
HPCA '97 Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
A Flow Control Mechanism to Avoid Message Deadlock in k-ary n-cube Networks
HIPC '97 Proceedings of the Fourth International Conference on High-Performance Computing
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Studying the Influence of the InfiniBand Packet Size to Guarantee QoS
ISCC '05 Proceedings of the 10th IEEE Symposium on Computers and Communications
POWER5 System microarchitecture
IBM Journal of Research and Development - POWER5 and packaging
Hardware support for WCET analysis of hard real-time multicore systems
Proceedings of the 36th annual international symposium on Computer architecture
POWER4 system microarchitecture
IBM Journal of Research and Development
aelite: a flit-synchronous network on chip with composable and predictable services
Proceedings of the Conference on Design, Automation and Test in Europe
Characterizing the Influence of System Noise on Large-Scale Applications by Simulation
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds
ECRTS '11 Proceedings of the 2011 23rd Euromicro Conference on Real-Time Systems
RTSS '11 Proceedings of the 2011 IEEE 32nd Real-Time Systems Symposium
An Analyzable Memory Controller for Hard Real-Time CMPs
IEEE Embedded Systems Letters
A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems
NOCS '12 Proceedings of the 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip
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Rings have been extensively used in high-performance systems to improve performance and scalability, and to reduce cost, energy and design effort. However, in the real-time domain, they have not been thoroughly analyzed to provide worst-case time bounds. We propose several on-chip ring designs in shared-memory multicore processors that enable the computation of trustworthy upper bounds to the time required for a packet to traverse the ring, which is a fundamental requirement to enable their use in real-time systems.