Low-level router design and its impact on supercomputer system performance
ICS '99 Proceedings of the 13th international conference on Supercomputing
A General Theory for Deadlock-Free Adaptive Routing Using a Mixed Set of Resources
IEEE Transactions on Parallel and Distributed Systems
Modeling of interconnection subsystems for massively parallel computers
Performance Evaluation
Impact of the Head-of-Line Blocking on Parallel Computer Networks: Hardware to Applications
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
On the Design of a High-Performance Adaptive Router for CC-NUMA Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
A first glance at Kilo-instruction based multiprocessors
Proceedings of the 1st conference on Computing frontiers
A Memory-Effective Routing Strategy for Regular Interconnection Networks
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
Evaluating kilo-instruction multiprocessors
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
A Routing Methodology for Achieving Fault Tolerance in Direct Networks
IEEE Transactions on Computers
High-performance adaptive routing for networks with arbitrary topology
Journal of Systems Architecture: the EUROMICRO Journal
FIR: an efficient routing strategy for tori and meshes
Journal of Parallel and Distributed Computing - 19th International parallel and distributed processing symposium
Throughput fairness in k-ary n-cube networks
ACSC '06 Proceedings of the 29th Australasian Computer Science Conference - Volume 48
FRoots: A Fault Tolerant and Topology-Flexible Routing Technique
IEEE Transactions on Parallel and Distributed Systems
A routing methodology for dynamic fault tolerance in meshes and tori
HiPC'07 Proceedings of the 14th international conference on High performance computing
Prevention flow-control for low latency torus Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
On-chip ring network designs for hard-real time systems
Proceedings of the 21st International conference on Real-Time Networks and Systems
Deadlock-free routing mechanism for 3D twin torus networks
Proceedings of the 8th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
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In this paper we propose a flow control algorithm fork-ary n-cube networks which avoids the deadlock problemswithout using virtual channels. Some basic definitionsand theorems are proposed in order to establish the necessaryand sufficient conditions to verify that an algorithmis deadlock-free. Our proposal is based on a restrictionof the virtual cut-through flow control rather than of therouting algorithm and it can be applied both over centralbuffers or edge buffers. A minimum free buffer space oftwo packets is required. The implementation complexity ofthe router, according to Chien's model, is much easier andfaster than using virtual channels. Network simulationsconsidering the router complexity show the performanceachieved by this new algorithm. The results display a latencyimprovement of 20% to 35% compared with the useof virtual channels depending on the load of the network.