ACM Transactions on Computer Systems (TOCS)
Communications of the ACM - Special section on computer architecture
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Multicomputer networks: message-based parallel processing
Multicomputer networks: message-based parallel processing
Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
Network and processor architecture for message-driven computers
VLSI and parallel computation
The Stanford Dash Multiprocessor
Computer
Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches
IEEE Transactions on Computers
The network architecture of the Connection Machine CM-5 (extended abstract)
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
The design of the Caltech Mosaic C multicomputer
Proceedings of the 1993 symposium on Research on integrated systems
A family of routing and communication chips based on the Mosaic
Proceedings of the 1993 symposium on Research on integrated systems
IBM Systems Journal
Petri net modeling of interconnection networks for massively parallel architectures
ICS '95 Proceedings of the 9th international conference on Supercomputing
ACM SIGARCH Computer Architecture News
Petri Net Theory and the Modeling of Systems
Petri Net Theory and the Modeling of Systems
Assessing the Performance of the New IBM SP2 Communication Subsystem
IEEE Parallel & Distributed Technology: Systems & Technology
Creating Simulation Capabilities
IEEE Computational Science & Engineering
Spider: A High-Speed Network Interconnect
IEEE Micro
Hypercube Communication Delay with Wormhole Routing
IEEE Transactions on Computers
Limits on Interconnection Network Performance
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Performance Analysis of Mesh Interconnection Networks with Deterministic Routing
IEEE Transactions on Parallel and Distributed Systems
On Petri nets with deterministic and exponentially distributed firing times
Advances in Petri Nets 1987, covers the 7th European Workshop on Applications and Theory of Petri Nets
A Simple Simulator for Multicomputer Routing Networks
A Simple Simulator for Multicomputer Routing Networks
A Critique of Adaptive Routing
A Critique of Adaptive Routing
A Flow Control Mechanism to Avoid Message Deadlock in k-ary n-cube Networks
HIPC '97 Proceedings of the Fourth International Conference on High-Performance Computing
Communication nets; stochastic message flow and delay
Communication nets; stochastic message flow and delay
A new modelling approach of wormhole-switched networks with finite buffers
International Journal of Parallel, Emergent and Distributed Systems
Computers and Electrical Engineering
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The analysis, design and evaluation of the interconnection subsystem for massively parallel architectures is normally carried out using computer simulation tools, requiring elevated computational costs. Moreover, in some cases, these simulation processes show serious difficulties when both experiments and results have to be reproduced by other research or design teams. This work shows the suitability of the use of formal representation methods, like DSPN (stochastic Petri nets with deterministic and exponential firing times), for the description of the message routers, focusing on two important features. Firstly, the possibility of obtaining network performance indicators through the simulation of the obtained models with a lower computational cost than using conventional techniques; in some cases, analytical results can also be obtained. And secondly, making the basic parameters of the network design relatively independent of the router implementation features, thus simplifying the method of establishing the behavior of new router structures. This approach has been successfully applied to the analysis of both symmetrical torus and asymmetrical mesh interconnection topologies, with virtual cut-through flow control, oblivious routing and random traffic. It should be noted that most modern parallel computers employ a local buffer space big enough to store at least a complete packet. Two different functional router structures have been used in each case: transit buffers located at the input or at the output router links.