Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Reliable and Precise WCET Determination for a Real-Life Processor
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Checking Safety Properties of Behavioral VHDL Descriptions by Abstract Interpretation
SAS '02 Proceedings of the 9th International Symposium on Static Analysis
Semi-automatic derivation of timing models for WCET analysis
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
New developments in WCET analysis
Program analysis and compilation, theory and practice
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Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the execution history sensitive behavior of components like caches, pipelines, buffers and periphery, the static determi-nation of safe upper execution-time bounds is a challenging task.A successful timing analysis approach developed at Saarland University/AbsInt GmbH uses abstract interpretation to derive safe WCET bounds based on timing models of the processor and periphery in a system. So far, WCET research has focused on processor timing behavior. System performance depends heavily on the performance of the periphery, namely the system controller, which includes the memory access logic. This paper is the first to describe experience in deriving a timing model for such a system con-troller. The starting point is the VHDL description from which the controllers FPGA implementation is synthesized. By a sequence of simplifications and abstractions we obtain an abstract VHDL model which can be translated easily into a timing model.The evaluation of the derived WCET tool shows that the approach leads to a precise and efficient analysis. This opens up the perspective of automatically deriving timing models from VHDL descriptions also for processors.