Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
Cache behavior prediction by abstract interpretation
Science of Computer Programming
Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
Reliable and Precise WCET Determination for a Real-Life Processor
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
IBM Journal of Research and Development
The Worst Case Execution Time Tool Challenge 2006: The External Test
ISOLA '06 Proceedings of the Second International Symposium on Leveraging Applications of Formal Methods, Verification and Validation
Improving the First-Miss Computation in Set-Associative Instruction Caches
ECRTS '08 Proceedings of the 2008 Euromicro Conference on Real-Time Systems
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New developments in WCET analysis
Program analysis and compilation, theory and practice
Cache persistence analysis: Theory and practice
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
FIFO cache analysis for WCET estimation: a quantitative approach
Proceedings of the Conference on Design, Automation and Test in Europe
WCET analysis with MRU cache: Challenging LRU for predictability
ACM Transactions on Embedded Computing Systems (TECS)
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To compute a worst-case execution time (WCET) estimate for a program, the architectural effects of the underlying hardware must be modeled. For modern processors this results in the need for a cache and pipeline analysis. The timing-relevant result of the cache analysis is the categorization of the accesses to cached memory. Categorizations that are obtainable by the well-known must and may cache analysis are always-hit, always-miss and not-classified. The cache persistence analysis tries to provide additional information for the not-classified case to limit the number of misses. There exists a cache persistence analysis by Ferdinand and Wilhelm based on abstract interpretation computing these classifications. In this paper, we present a correctness issue with this analysis and a novel analysis that fixes it. For fully timing compositional architectures the persistence information is straightforward to use. We will focus on the application of the persistence analysis for state-of-the-art architectures that show timing anomalies. Such architectures do not allow to quantify the costs of a single cache hit or miss in isolation. To make the usage of the persistence information feasible, we integrate the novel persistence analysis together with a novel path analysis approach into the industrially used WCET analyzer aiT.