Program optimization for instruction caches
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Achieving high instruction cache performance with an optimizing compiler
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Profile guided code positioning
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
Reducing branch costs via branch alignment
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Near-optimal intraprocedural branch alignment
Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
Reliable and Precise WCET Determination for a Real-Life Processor
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Timing Analysis for Data Caches and Set-Associative Caches
RTAS '97 Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97)
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
RTSS '04 Proceedings of the 25th IEEE International Real-Time Systems Symposium
Automatic Timing Model Generation by CFG Partitioning and Model Checking
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Real-Time Scheduling on Multicore Platforms
RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
Hybrid multi-core architecture for boosting single-threaded performance
ACM SIGARCH Computer Architecture News
Soft Real-Time Scheduling on Performance Asymmetric Multicore Platforms
RTAS '07 Proceedings of the 13th IEEE Real Time and Embedded Technology and Applications Symposium
A Hybrid Real-Time Scheduling Approach for Large-Scale Multicore Platforms
ECRTS '07 Proceedings of the 19th Euromicro Conference on Real-Time Systems
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
RTAS '08 Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium
WCET-driven Cache-based Procedure Positioning Optimizations
ECRTS '08 Proceedings of the 2008 Euromicro Conference on Real-Time Systems
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Unlike general-purpose programs, it is important to reduce the worst-case performance rather than the average-case performance for real-time systems. In this paper, based on a dual-core processor with a shared L2 cache, we propose a code positioning scheme that can reduce the worst-case execution time (WCET) for real-time threads by minimizing both the intra-thread and inter-thread instruction cache misses. Our experiments indicate that the proposed hybrid code positioning approach can effectively reduce the worst-case performance for real-time threads running on this dual-core processor.