Real-Time Scheduling on Multicore Platforms

  • Authors:

  • James H. Anderson;John M. Calandrino;UmaMaheswari C. Devi

  • Affiliations:

  • The University of North Carolina at Chapel Hill;The University of North Carolina at Chapel Hill;The University of North Carolina at Chapel Hill

  • Venue:
  • RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
  • Year:
  • 2006

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Abstract

Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance, given that thermal and power problems impose limits on the performance of single-core designs. Accordingly, several chip manufacturers have already released, or will soon release, chips with dual cores, and it is predicted that chips with up to 32 cores will be available within a decade. To effectively use the available processing resources on multicore platforms, software designs should avoid co-executing applications or threads that can worsen the performance of shared caches, if not thrash them. While cache-aware scheduling techniques for such platforms have been proposed for throughput-oriented applications, to the best of our knowledge, no such work has targeted real-time applications. In this paper, we propose and evaluate a cache-aware Pfair-based scheduling scheme for real-time tasks on multicore platforms