Noise considerations in circuit optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Technology trends in power-grid-induced noise
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
High-level current macro-model for power-grid analysis
Proceedings of the 39th annual Design Automation Conference
An "effective" capacitance based delay metric for RC interconnect
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Real-Time Scheduling on Multicore Platforms
RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
Basic Electric Circuit Analysis
Basic Electric Circuit Analysis
Power Management of Multicore Multiple Voltage Embedded Systems by Task Scheduling
ICPPW '07 Proceedings of the 2007 International Conference on Parallel Processing Workshops
POWER4 system microarchitecture
IBM Journal of Research and Development
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As the industry moves from single- to multi-core processors, the challenges of how to reliably design and analyze power delivery for such systems also arise. We study various workload assignments to cores and their impact on the global power grid noise. We develop metrics to estimate the amount of noise propagated from core to core and propose a power supply noise aware workload assignment method. In our experiments, we show that performance loss can be significant if workload assignment is not properly made.