Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems
WCET-aware register allocation based on graph coloring
Proceedings of the 46th Annual Design Automation Conference
Multicore-aware hybrid code positioning to reduce worst-case execution time
Proceedings of the 2010 Workshop on Interaction between Compilers and Computer Architecture
A compiler framework for the reduction of worst-case execution times
Real-Time Systems
WCET-driven cache-aware code positioning
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Cache-Aware development of high-integrity systems
Ada-Europe'10 Proceedings of the 15th Ada-Europe international conference on Reliable Software Technologies
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
Optimising task layout to increase schedulability via reduced cache related pre-emption delays
Proceedings of the 20th International Conference on Real-Time and Network Systems
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Procedure Positioning is a well known compiler opti-mization aiming at the improvement of the instruction cachebehavior. A contiguous mapping of procedures callingeach other frequently in the memory avoids overlapping ofcache lines and thus decreases the number of cache conflictmisses. In standard literature, these positioning techniquesare guided by execution profile data and focus on an im-proved average-case performance.We present two novel positioning optimizations drivenby worst-case execution time (WCET) information to effec-tively minimize the program's worst-case behavior. WCETreductions by 10% on average are achieved. Moreover, acombination of positioning and the WCET-driven Proce-dure Cloning optimization proposed in [14] is presented im-proving the WCET analysis by 36% on average.