Timing Analysis of Assembler Code Control-Flow Paths

Authors:
Colin J. Fidge
Affiliations:
-
Venue:
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
Year:
2002

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Abstract

Timing analysis of assembler code is essential to achieve the strongest possible guarantee of correctness for safety-critical, real-time software. Previous work has shown how timing constraints on control-flow paths through high-level language programs can be formalised using the semantics of the statements comprisingthe path. We extend these results to assembler-level code where it becomes possible to not only determine timing constraints, but also to verify them against the known execution times for each instruction. A minimal formal model is developed with both a weakest liberal precondition and a strongest postcondition semantics. However, despite the formalism's simplicity, it is shown that complex timing behaviour associated with instruction pipelining and iterative code can be modelled accurately.