Chip-size evaluation of a multithreaded processor enhanced with a PID controller

Authors:
Michael Bauer;Mathias Pacher;Uwe Brinkschulte
Affiliations:
Embedded Systems, Goethe-University Frankfurt am Main, Germany;Embedded Systems, Goethe-University Frankfurt am Main, Germany;Embedded Systems, Goethe-University Frankfurt am Main, Germany
Venue:
SEUS'10 Proceedings of the 8th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems
Year:
2010

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Abstract

In this paper the additional chip size of a Proportional/Integral/Differential (PID) controller in a multithreaded processor is evaluated. The task of the PID unit is to stabilize a thread's throughput, the instruction per cycle rate (IPC rate). The stabilization of the IPC rate allocated to the main thread increases the efficiency of the processor and also the execution time remaining for other threads. The overhead introduced by the PID controller implementation in the VHDL model of an embedded Java real-time-system is examined.