The ARISE approach for extending embedded processors with arbitrary hardware accelerators

  • Authors:

  • Nikolaos Vassiliadis;George Theodoridis;Spiridon Nikolaidis

  • Affiliations:

  • Electronics and Computers Section, Physics Department, Aristotle University of Thessaloniki, Thessaloniki, Greece;Electronics and Computers Section, Physics Department, Aristotle University of Thessaloniki, Thessaloniki, Greece;Electronics and Computers Section, Physics Department, Aristotle University of Thessaloniki, Thessaloniki, Greece

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2009

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Abstract

ARISE introduces a systematic approach for extending once an embedded processor to support thereafter the coupling of an arbitrary number of custom computing units (CCUs). A CCU can be a hardwired or a reconfigurable unit, which can be utilized following a tight and/or loose model of computation. By selecting the appropriate model of computation for each part of the application, the complete application space is considered for acceleration, resulting in significant performance improvements. Also, ARISE offers modularity and scalability and is not restricted by the opcode space and operands limitation problems that exist in such type of machines. To support these features we introduce a machine organization that allows the cooperation of a processor and a set of CCUs. To control the CCUs we extend once the instruction set of the processor with eight instructions. To efficiently incorporate these features to an embedded processor, we propose a micro-architecture implementation that minimizes the control and communication overhead between the processor and the CCUs. To evaluate our proposal, we extended a MIPS processor with the ARISE infrastructure and implemented it on a Xilinx field-programmable gate array (FPGA). Implementation results, demonstrate that the timing model of the processor is not affected. Also, we implemented a set of benchmarks on the ARISE evaluation machine. Performance results prove significant improvements and reduced communication overhead compared to a typical coprocessor approach.