DPGA utilization and application
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
MorphoSys: case study of a reconfigurable computing system targeting multimedia applications
Proceedings of the 37th Annual Design Automation Conference
Design space characterization for architecture/compiler co-exploration
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Computer Architecture: Complexity and Correctness
Computer Architecture: Complexity and Correctness
Architecture Exploration for Embedded Processors with Lisa
Architecture Exploration for Embedded Processors with Lisa
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
PACT XPP—A Self-Reconfigurable Data Processing Architecture
The Journal of Supercomputing
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Modeling and validation of pipeline specifications
ACM Transactions on Embedded Computing Systems (TECS)
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams
Proceedings of the 31st annual international symposium on Computer architecture
The ArchC architecture description language and tools
International Journal of Parallel Programming
Architectural exploration of the ADRES coarse-grained reconfigurable array
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Rapid functional modelling and simulation of coarse grained reconfigurable array architectures
Journal of Systems Architecture: the EUROMICRO Journal
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The high degree of freedom in the design of coarse-grained reconfigurable arrays imposes new challenges on their description and modeling. In this paper, we introduce an architecture description language targeted to describe coarse-grained reconfigurable architecture templates. It comprises innovative key features to allow fast modeling and analysis of such architectures, i.e.: representation of processing element array (ir)regularities, and flexible and concise description of interconnection network. We demonstrate that the proposed language enables a formal validation of the described template, and it eases the analysis and estimation of hardware costs earlier in the design phase. Finally, we show how we automatically generate a SystemC-based simulator of the described architecture. Our results suggest that the semantic and technical innovations of the proposed architecture description language may have a positive impact on the productivity of the design phase.