Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator
DAC '98 Proceedings of the 35th annual Design Automation Conference
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Combining Abstract Interpretation and ILP for Microarchitecture Modelling and Program Path Analysis
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
C Compiler Retargeting Based on Instruction Semantics Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
The ArchC architecture description language and tools
International Journal of Parallel Programming
A Retargetable Software Timing Analyzer Using Architecture Description Language
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Performance analysis of embedded software using implicit path enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISoLA'10 Proceedings of the 4th international conference on Leveraging applications of formal methods, verification, and validation - Volume Part I
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With the demand for energy-efficient embedded computing and the rise of heterogeneous architectures, automatically retargetable techniques are likely to grow in importance. On the one hand, retargetable compilers do not handle real-time constraints properly. On the other hand, conventional worst-case execution time (WCET) approaches are not automatically retargetable: measurement-based methods require time-consuming dynamic characterization of target processors, whereas static program analysis and abstract interpretation are performed in a post-compiling phase, being therefore restricted to the set of supported targets. This paper proposes a retargetable technique to grant early real-time checking (ERTC) capabilities for design space exploration. The technique provides a general (minimum, maximum and exact-delay) timing analysis at compile time. It allows the early detection of inconsistent time-constraint combinations prior to the generation of binary executables, thereby promising higher design productivity. ERTC is a complement to state-of-the-art design flows, which could benefit from early infeasiblity detection and exploration of alternative target processors, before the binary executables are submitted to tight-bound BCET and WCET analyses for the selected target processor.