Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation

Authors:
In-Cheol Park;Sehyeon Kang;Yongseok Yi
Affiliations:
KAIST - Daejeon, Korea;KAIST - Daejeon, Korea;KAIST - Daejeon, Korea
Venue:
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Year:
2003

Citing 11
Cited 2

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Abstract

Modeling and simulating pipelined processors in procedurallanguages such as C/C++ requires lots of cost in handlingconcurrent events, which hinders fast simulation. A number ofresearches on simulation have devised speed-up techniques toreduce the number of events. This paper presents a newsimulation approach developed to enhance the simulation ofpipelined processors. The proposed approach is based on earlypipeline evaluation that all the intermediate values of aninstruction are computed in advance, creating a future state for thenext instructions. The future state allows the next instructions tobe computed without considering data dependencies betweennearby instructions. We apply this concept to building a cycle-accurate simulator for a pipelined RISC processor and achieve almost the same speed as the instruction-level simulator.