Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse

Computer architecture: a quantitative approach

Computer architecture: a quantitative approach

Software timing analysis using HW/SW cosimulation and instruction set simulator

Proceedings of the 6th international workshop on Hardware/software codesign

A universal technique for fast and flexible instruction-set architecture simulation

Proceedings of the 39th annual Design Automation Conference

An ultra-fast instruction set simulator

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Trace-driven rapid pipeline architecture evaluation scheme for ASIP design

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems