Detecting pipeline structural hazards quickly
POPL '94 Proceedings of the 21st ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Shade: a fast instruction-set simulator for execution profiling
SIGMETRICS '94 Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Efficient instruction scheduling using finite state automata
International Journal of Parallel Programming - Special issue on instruction-level parallel processing—part I
Fast out-of-order processor simulation using memoization
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Resource usage models for instruction scheduling: two new models and a classification
ICS '99 Proceedings of the 13th international conference on Supercomputing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Retargetable compiled simulation of embedded processors using a machine description language
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Facile: a language and compiler for high-performance processor simulators
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Microprocessor Architectures: From VLIW to Tta
Microprocessor Architectures: From VLIW to Tta
Introduction to Algorithms
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Proceedings of the 42nd annual Design Automation Conference
DynamoSim: a trace-based dynamically compiled instruction set simulator
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Trace-driven rapid pipeline architecture evaluation scheme for ASIP design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A fast and generic hybrid simulation approach using C virtual machine
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Hi-index | 0.00 |
Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating architectures with independent function unit pipelines using simulation techniques that avoid the overhead of instruction bit-string interpretation, such as compiled simulation, the simulation of function unit pipelines can become one of the new bottlenecks for simulation speed. This paper evaluates several resource conflict detection models, commonly used in compiler instruction scheduling, in the context of function unit pipeline simulation. The evaluated models include the conventional reservation table based-model, the dynamic collision matrix model, and an finite state automata (FSA) based model. In addition, an improvement to the simulation initialization time by means of lazy initialization of states in the FSA-based approach is proposed. The resulting model is faster to initialize and provides comparable simulation speed to the actively initialized FSA.