High-level automatic pipelining for sequential circuits
Proceedings of the 14th international symposium on Systems synthesis
Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
High-level optimization of pipeline design
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Simulation vs. formal: absorb what is useful; reject what is useless
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
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Abstract: This paper introduces a new specification style for processor microarchitectures. Our goal is to produce very simple, compact, but cycle-accurate descriptions, in order to enable early exploration of different microarchitectures and their performance. The key idea behind our approach is that we can derive the difficult-to-design forwarding and stall logic completely automatically. We have implemented a specification language for pipelined processors, along with an automatic translator that creates cycle-accurate software simulators from the specifications. We have specified a pipelined MIPS integer core in our language. The entire specification is less than 300 lines long and implements all user-mode instructions except for coprocessor support. The resulting, automatically-generated, cycle-accurate simulator achieves over 240,000 instructions per second simulating MIPS machine code. This performance is within an order of magnitude of large, hand-crafted, cycle-accurate simulators, but our specification is far easier to create, read, and modify.