Integrated Verification Approach during ADL-Driven Processor Design

  • Authors:

  • Anupam Chattopadhyay;Arnab Sinha;Diandian Zhang;Rainer Leupers;Gerd Ascheid;Heinrich Meyr

  • Affiliations:

  • Aachen University of Technology, Germany;Indian Institute of Technology, India;Aachen University of Technology, Germany;Aachen University of Technology, Germany;Aachen University of Technology, Germany;Aachen University of Technology, Germany

  • Venue:
  • RSP '06 Proceedings of the Seventeenth IEEE International Workshop on Rapid System Prototyping
  • Year:
  • 2006

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Abstract

Nowadays, Architecture Description Languages (ADLs) are getting popular to achieve quick and optimal design convergence during the development of Application Specific Instruction-Set Processors (ASIPs). Verification, in various stages of such ASIP development, is a major bottleneck hindering widespread acceptance of ADL-based processor design approach. Traditional verification of processors are only applied at Register Transfer Level (RTL) or below. In the context of ADL-based ASIP design, this verification approach is often inconvenient and error-prone, since design and verification are done at different levels of abstraction. In this paper, this problem is addressed by presenting an integrated verification approach during ADL-driven processor design. Our verification flow includes the idea of automatic assertion generation during high-level synthesis and support for automatic test-generation utilizing the ADL-framework for ASIP design. We show the benefit of our approach by trapping errors in a pipelined SPARC-compliant processor architectur