Automatic synthesis of state machines from trace diagrams
Software—Practice & Experience
DIPES '98 Proceedings of the IFIP WG10.3/WG10.5 international workshop on Distributed and parallel embedded systems
Come, Let's Play: Scenario-Based Programming Using LSC's and the Play-Engine
Come, Let's Play: Scenario-Based Programming Using LSC's and the Play-Engine
LSCs: Breathing Life into Message Sequence Charts
LSCs: Breathing Life into Message Sequence Charts
Revisiting Statechart Synthesis with an Algebraic Approach
Proceedings of the 26th International Conference on Software Engineering
A comparative survey of scenario-based to state-based model synthesis approaches
Proceedings of the 2006 international workshop on Scenarios and state machines: models, algorithms, and tools
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In the field of hardware development, it is essential to prove the correctness of a new design. In order to check a design, verification engineers often use assertions written in a property or hardware specification language. Sequence diagrams are well established in the field of software engineering and allow easy and compact specification of protocols. We propose to use sequence diagrams to specify register transfer level (RTL) behaviour and present an approach to automatically generate temporal properties out of these diagrams. The validity of the approach is illustrated by verifying a Wishbone system-on-a-chip (SoC) local interconnect bus.